1. Field of the Invention
The invention relates generally to testing of integrated circuits and, in particular, to a method and structure for chip-level testing of wire delay.
2. Description of the Related Art
Metal wire variation affects the capacitance and resistance of a wire interconnects and thereby significantly impacts the timing of semiconductor chips. As scaling of integrated circuit technologies increases so does the role that wire delay plays on overall integrated circuit delay. Metal lines are processed independently on different metal levels such that the resistance-capacitance delay on each metal layer may vary and thus, each resistance-capacitance delay on each level should be monitored. In-Line Kerf monitors are used today to periodically monitor parameters such as resistance or capacitance, independently, on semiconductor wafers. These monitors do not specifically measure wire delay. Additionally, the measurements taken by in-line Kerf monitors are gross measurements which simply indicate when the overall measured parameter for a wafer is wildly out of spec. These in-line Kerf measurements are designed for manufacturing process centering and are not used to make pass/fail decisions regarding an entire wafer based upon resistance or capacitance. However, because they do not measure delay directly and because they can not isolate a location of the delay to a particular chip or metal layer on a chip, they are not suitable for making chip-level pass/fail decisions.